/*
Copyright (C) 2018-2019 de4dot@gmail.com

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

use wasm_bindgen::prelude::*;

// GENERATOR-BEGIN: Enum
// ⚠️This was generated by GENERATOR!🦹‍♂️
/// Decoder options
#[wasm_bindgen]
#[derive(Copy, Clone)]
#[allow(non_camel_case_types)]
pub enum DecoderOptions {
	/// No option is enabled
	None = 0x0000_0000,
	/// Disable some checks for invalid encodings of instructions, eg. most instructions can't use a `LOCK` prefix so if one is found, they're decoded as [`Code.INVALID`] unless this option is enabled.
	///
	/// [`Code.INVALID`]: enum.Code.html#variant.INVALID
	NoInvalidCheck = 0x0000_0001,
	/// AMD branch decoder: allow 16-bit branch/ret instructions in 64-bit mode
	AmdBranches = 0x0000_0002,
	/// Decode opcodes `0F0D` and `0F18-0F1F` as reserved-nop instructions (eg. [`Code.ReservedNop_rm32_r32_0F1D`])
	///
	/// [`Code.ReservedNop_rm32_r32_0F1D`]: enum.Code.html#variant.ReservedNop_rm32_r32_0F1D
	ForceReservedNop = 0x0000_0004,
	/// Decode `UMOV` instructions (eg. [`Code.Umov_r32_rm32`])
	///
	/// [`Code.Umov_r32_rm32`]: enum.Code.html#variant.Umov_r32_rm32
	Umov = 0x0000_0008,
	/// Decode `XBTS`/`IBTS`
	Xbts = 0x0000_0010,
	/// Decode `0FA6`/`0FA7` as `CMPXCHG`
	Cmpxchg486A = 0x0000_0020,
	/// Decode some old removed FPU instructions (eg. `FRSTPM`)
	OldFpu = 0x0000_0040,
	/// Decode [`Code.Pcommit`]
	///
	/// [`Code.Pcommit`]: enum.Code.html#variant.Pcommit
	Pcommit = 0x0000_0080,
	/// Decode 286 `LOADALL` (`0F04` and `0F05`)
	Loadall286 = 0x0000_0100,
	/// Decode [`Code.Loadall386`]
	///
	/// [`Code.Loadall386`]: enum.Code.html#variant.Loadall386
	Loadall386 = 0x0000_0200,
	/// Decode [`Code.Cl1invmb`]
	///
	/// [`Code.Cl1invmb`]: enum.Code.html#variant.Cl1invmb
	Cl1invmb = 0x0000_0400,
	/// Decode [`Code.Mov_r32_tr`] and [`Code.Mov_tr_r32`]
	///
	/// [`Code.Mov_r32_tr`]: enum.Code.html#variant.Mov_r32_tr
	/// [`Code.Mov_tr_r32`]: enum.Code.html#variant.Mov_tr_r32
	MovTr = 0x0000_0800,
	/// Decode `JMPE` instructions
	Jmpe = 0x0000_1000,
	/// Don't decode [`Code.Pause`], decode [`Code.Nopd`]/etc instead
	///
	/// [`Code.Pause`]: enum.Code.html#variant.Pause
	/// [`Code.Nopd`]: enum.Code.html#variant.Nopd
	NoPause = 0x0000_2000,
	/// Don't decode [`Code.Wbnoinvd`], decode [`Code.Wbinvd`] instead
	///
	/// [`Code.Wbnoinvd`]: enum.Code.html#variant.Wbnoinvd
	/// [`Code.Wbinvd`]: enum.Code.html#variant.Wbinvd
	NoWbnoinvd = 0x0000_4000,
	/// Don't decode `LOCK MOV CR0` as `MOV CR8` (AMD)
	NoLockMovCR0 = 0x0000_8000,
	/// Don't decode [`Code.Tzcnt_r32_rm32`]/etc, decode [`Code.Bsf_r32_rm32`]/etc instead
	///
	/// [`Code.Tzcnt_r32_rm32`]: enum.Code.html#variant.Tzcnt_r32_rm32
	/// [`Code.Bsf_r32_rm32`]: enum.Code.html#variant.Bsf_r32_rm32
	NoMPFX_0FBC = 0x0001_0000,
	/// Don't decode [`Code.Lzcnt_r32_rm32`]/etc, decode [`Code.Bsr_r32_rm32`]/etc instead
	///
	/// [`Code.Lzcnt_r32_rm32`]: enum.Code.html#variant.Lzcnt_r32_rm32
	/// [`Code.Bsr_r32_rm32`]: enum.Code.html#variant.Bsr_r32_rm32
	NoMPFX_0FBD = 0x0002_0000,
	/// Don't decode [`Code.Lahf`] and [`Code.Sahf`] in 64-bit mode
	///
	/// [`Code.Lahf`]: enum.Code.html#variant.Lahf
	/// [`Code.Sahf`]: enum.Code.html#variant.Sahf
	NoLahfSahf64 = 0x0004_0000,
}
// GENERATOR-END: Enum
